Low Power in Nano-scale Cmos Memory
نویسنده
چکیده
Future technologies required nano-scale CMOS memory to be operating in low power consumption. The minimum operating voltage of the nano-scale CMOS played as a main factor to reduce the power consumption. Consequently, there are some limitations and obstacles to achieve the objective for several design, material and novel structural solutions, which are promising and reliable. In this research, the noticeable limits, possible annexes and applications of CMOS technologies in the nanometer regime is discussed. This paper mainly describes the limitations that conventional MOSFET is faced. In addition, the solutions to low power in nano-scale CMOS memory are presented. Therefore, analysis of the attainable performance and potential restrictions of CMOS technologies from the point of design, material and structural solution techniques are illustrated.
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